Kaminario has introduced the 4th generation of its K2 enterprise-grade storage array. Unlike the company’s earlier K2s, which supported DRAM, SSD, and HDD, the fourth generation K2 is all-flash, based on SAS SSDs alone. The company says that its new approach reduces the cost of ownership by supporting a larger capacity within a smaller footprint while requiring less power and cooling.
The SSDs are MLC products, rather than the SLC ones used in earlier K2s, allowing Kaminario to reduce the cost. Although the SSDs Kaminario uses come with a 5-year warranty, the K2′s SPEAR operating system optimizes flash endurance allowing Kaminario to offer a 7-year warranty. (SPEAR is Kaminario’s scale-out performance storage architecture operating system software.)
The original K2 was built with a focus on Continue reading
At last week’s International Solid State Circuits Conference (ISSCC) Shuhei Tanakamaru, a researcher from Japan’s Chuo University, detailed a scheme to reduce MLC SSD bit error rates (BER) by 32 times over conventional techniques. The approach used an impressive combination of mirroring, vertical and horizontal error correction, and a deep understanding of the most likely kinds of bit errors flash will experience.
This is a very novel and well-conceived technique that may find industry adoption in future SSDs.
The steps included in the paper are used in addition to the Continue reading
Given that you have used all those other forms of improving SSD wear that we have discussed so far, but you still don’t find that this is enough, what do you do next? Well a few SSD controllers go one step further and manage some of the inner workings of the NAND flash chip itself.
If that sounds like a significant undertaking to you, then you clearly understand why so very few controllers take this approach. The information used to perform this function is not generally available – it takes a special relationship with the NAND flash supplier – and you can’t develop this relationship unless the NAND supplier Continue reading
One way that SSD controllers maximize the life of an SSD is to use feedback on the life of flash blocks to determine how wear has impacted them. Although this used to be very uncommon, it is now being incorporated into a number of controllers.
Here’s what this is all about: Everybody knows that endurance specifications tell how much life there is in a block, right? For SLC it is typically 100,000 erase/write cycles, and for MLC it can be as high as 10,000 cycles (for older processes) but goes down to 5,000 or even 3,000 for newer processes. TLC endurance can be in the hundreds of cycles. Now the question is: “What happens after that?”
In most cases individual bits start to Continue reading
Write amplification plays a critical role in maximizing an SSD’s usable life. The lower the write amplification, the longer the SSD will last. SSD architects pay special attention to this aspect of controller design.
Unlike the other factors described in this series this is not a technique that extends flash life beyond the 10,000 erase/write cycles that one would normally expect to result in a failure, but it is very important to SSD longevity.
Write Amplification is sufficiently complex that I won’t try to define it in this post, but Continue reading
There are more advanced means than simple error correction to help remove bit errors in NAND flash and those will be the subject of this post. The general term for this approach is “DSP” although it seems to have very little to do with the kind of DSP algorithm used to perform filtering or build modem chips.
While ECC corrects errors without knowing how they got there, DSP helps to correct any of the more predictable errors that are caused by internal error mechanisms that are inherent to the design of the chip. A prime example of such an error would be adjacent cell disturb.
Here’s a brief explanation of Continue reading
Error correction (ECC) can have a very big impact on the longevity of an SSD, although few understand how such a standard item can make much difference to an SSD’s life. The SSD Guy will try to explain it in relatively simple terms here.
All NAND flash requires ECC to correct random bit errors (“soft” errors.) This is because the inside of a NAND chip is very noisy and the signal levels of bits passed through a NAND string are very weak. One of the ways that NAND has been able to become the cheapest of all memories is by requiring error correction external to the chip.
This same error correction also helps to correct bit errors due to wear. Wear can cause bits to become stuck in one state or the other (a “hard” error), and it can increase the frequency of soft errors.
Although it is not widely Continue reading
Since NAND flash is weakened by erase/write cycles then it would make sense to try to reduce those cycles to prolong the life of an SSD right? That’s what external data buffers are designed to do.
There are many ways to use RAM (either a RAM internal to the SSD controller chip or a discrete DRAM chip on the SSD’s printed circuit card) to stage data in a way that will reduce erase/write cycles.
One is to perform a function called “Write Coalescing.” This involves Continue reading
Samsung on Monday introduced a new “840″ SSD series which reviewers have found is based on TLC flash.
Oddly enough the press release for this product seems only to have been distributed in Korea to reviewers who attended a special introduction of the device. The SSD Guy has not been given the specifications presented at the event, and had to ask Samsung for a copy of the press release.
The press release focuses on the product’s 100,000 read IOPS, that it comes in two versions, the “Pro” model for the enterprise and another model for client applications, and the fact that the controller uses a new design based on three ARM cores. A read IOPS figure of 100,000 is very high performance for a SATA drive! One has to wonder if the client market will be able to distinguish between this level of performance and drives with fewer than 10,000 IOPS.
Other specifications Continue reading
In this post we will explore how the right wear leveling algorithm can help a controller maximize the life of an SSD.
Wear leveling is a fact of life with NAND flash – blocks start to suffer bit failures after a certain number of erase/write cycles (usually specified from the thousands to the hundreds of thousands) and it is only natural that software will attempt to over-write some blocks more than others. In order to prevent this from causing failures, all of today’s SSD, USB flash drive, and flash card controllers incorporate some sort of wear leveling.
This is a simple re-mapping of the contents of the flash chips. A more graphical explanation is Continue reading