There are more advanced means than simple error correction to help remove bit errors in NAND flash and those will be the subject of this post. The general term for this approach is “DSP” although it seems to have very little to do with the kind of DSP algorithm used to perform filtering or build modem chips.
While ECC corrects errors without knowing how they got there, DSP helps to correct any of the more predictable errors that are caused by internal error mechanisms that are inherent to the design of the chip. A prime example of such an error would be adjacent cell disturb.
Here’s a brief explanation of Continue reading
In this post we will explore how the right wear leveling algorithm can help a controller maximize the life of an SSD.
Wear leveling is a fact of life with NAND flash – blocks start to suffer bit failures after a certain number of erase/write cycles (usually specified from the thousands to the hundreds of thousands) and it is only natural that software will attempt to over-write some blocks more than others. In order to prevent this from causing failures, all of today’s SSD, USB flash drive, and flash card controllers incorporate some sort of wear leveling.
This is a simple re-mapping of the contents of the flash chips. A more graphical explanation is Continue reading
How do controllers maximize the life of an SSD? After all, MLC flash has a lifetime of only 10,000 erase/write cycles or fewer and that is a very small number compared to the write traffic an SSD is expected to see in a high-workload environment, especially in the enterprise. Still, MLC is becoming the norm in the enterprise.
How do they do that?