Extreme SSD Error Correction

Chuo University EmblemAt last week’s International Solid State Circuits Conference (ISSCC) Shuhei Tanakamaru, a researcher from Japan’s Chuo University, detailed a scheme to reduce MLC SSD bit error rates (BER) by 32 times over conventional techniques.  The approach used an impressive combination of mirroring, vertical and horizontal error correction, and a deep understanding of the most likely kinds of bit errors flash will experience.

This is a very novel and well-conceived technique that may find industry adoption in future SSDs.

The steps included in the paper are used in addition to the Continue reading “Extreme SSD Error Correction”

New Booklet: How Controllers Maximize SSD Life

SNIA SSD Controller BookSNIA (The Storage Networking Industry Association) has conferred a great honor upon the SSD Guy by bringing all of the blog posts in the series How Controllers Maximize SSD Life into a single printed volume of the same name.

Readers can either ask for a print copy from SNIA, or can download a pdf rendition by visiting the SNIA SSSI (Solid State Storage Initiative) education web page.