An ReRAM SSD Design

Chuo University EmblemA colleague pointed The SSD Guy to an ExtremeTech article about researchers at Japan’s Chuo University who have designed an SSD that uses a resistive RAM (ReRAM) as a buffer and is built using TSV technology.  The design was presented at the IEEE’s 2012 Symposium on VLSI Circuits this month in Hawaii.  A Nikkei article gives additional information.

The basic architecture reminds me of an FRAM + NAND SSD design that a Korean university presented at the Flash Memory Summit a few years ago.  Either approach gets past the problem of using a failure-prone battery, a temperature-sensitive supercap, or a big bulky bank of tantalum capacitors to allow the SSD’s DRAM cache time to move data into flash in the event of a power failure.  One difference here is that the Chuo University design still uses a DRAM.  It’s unclear why a DRAM would be necessary in a circuit with an ReRAM.

One of the article’s graphics (taken directly from the conference proceedings) shows that the write energy drops significantly with TSV.  This is puzzling to me.  A write to NAND flash doesn’t put a lot of energy into I/O and I/O is where TSVs really help to reduce power loss. The article doesn’t make out that there’s any other reason to use TSV.

So far my inquiry to the developers has gone unanswered, but if they reply then I will update this post.

It’s too bad that the SSD design is based on two technologies (ReRAM & TSV) that are not yet in mass production! MRAM, FRAM, or PCM would be better choices that way, and I would imagine conventional packaging would work just fine.

Readers wanting to know more about the SSD market can purchase our report: Solid State Disk Market Outlook, which is available for immediate download from the Objective Analysis website.

2 thoughts on “An ReRAM SSD Design”

  1. Considering how many hundreds of millions of DRAM chips that are being produced daily, the answer is obvious, the dram manufacturers wish to off load any current stock before advertising ReRam (and other new tech) as the best thing since sliced bread.

    This dual technology chip, is also a test format prior to large scale production so these “performance chips” can also be priced up on the market making greater economic profit for less ReRam in circulation.

    It also stops the DRAM market from crashing , as everyone would rush to implement ReRam enabled devices if their implementation wasn’t controlled.

    This way is more measured and controllable

Leave a Reply

Your email address will not be published. Required fields are marked *

This site uses Akismet to reduce spam. Learn how your comment data is processed.