There are more advanced means than simple error correction to help remove bit errors in NAND flash and those will be the subject of this post. The general term for this approach is “DSP” although it seems to have very little to do with the kind of DSP algorithm used to perform filtering or build modem chips.
While ECC corrects errors without knowing how they got there, DSP helps to correct any of the more predictable errors that are caused by internal error mechanisms that are inherent to the design of the chip. A prime example of such an error would be adjacent cell disturb.
Here’s a brief explanation of Continue reading “How Controllers Maximize SSD Life – Other Error Management”
Error correction (ECC) can have a very big impact on the longevity of an SSD, although few understand how such a standard item can make much difference to an SSD’s life. The SSD Guy will try to explain it in relatively simple terms here.
All NAND flash requires ECC to correct random bit errors (“soft” errors.) This is because the inside of a NAND chip is very noisy and the signal levels of bits passed through a NAND string are very weak. One of the ways that NAND has been able to become the cheapest of all memories is by requiring error correction external to the chip.
This same error correction also helps to correct bit errors due to wear. Wear can cause bits to become stuck in one state or the other (a “hard” error), and it can increase the frequency of soft errors.
Although it is not widely Continue reading “How Controllers Maximize SSD Life – Improved ECC”
Since NAND flash is weakened by erase/write cycles then it would make sense to try to reduce those cycles to prolong the life of an SSD right? That’s what external data buffers are designed to do.
There are many ways to use RAM (either a RAM internal to the SSD controller chip or a discrete DRAM chip on the SSD’s printed circuit card) to stage data in a way that will reduce erase/write cycles.
One is to perform a function called “Write Coalescing.” This involves Continue reading “How Controllers Maximize SSD Life – External Data Buffering”
In this post we will explore how the right wear leveling algorithm can help a controller maximize the life of an SSD.
Wear leveling is a fact of life with NAND flash – blocks start to suffer bit failures after a certain number of erase/write cycles (usually specified from the thousands to the hundreds of thousands) and it is only natural that software will attempt to over-write some blocks more than others. In order to prevent this from causing failures, all of today’s SSD, USB flash drive, and flash card controllers incorporate some sort of wear leveling.
This is a simple re-mapping of the contents of the flash chips. A more graphical explanation is Continue reading “How Controllers Maximize SSD Life – Better Wear Leveling”
How do controllers maximize the life of an SSD? After all, MLC flash has a lifetime of only 10,000 erase/write cycles or fewer and that is a very small number compared to the write traffic an SSD is expected to see in a high-workload environment, especially in the enterprise. Still, MLC is becoming the norm in the enterprise.
How do they do that?
This is where SSD architects really earn their pay. There are eight basic techniques that The SSD Guy knows of to extend SSD life beyond Continue reading “How Controllers Maximize SSD Life”
A colleague pointed The SSD Guy to an ExtremeTech article about researchers at Japan’s Chuo University who have designed an SSD that uses a resistive RAM (ReRAM) as a buffer and is built using TSV technology. The design was presented at the IEEE’s 2012 Symposium on VLSI Circuits this month in Hawaii. A Nikkei article gives additional information.
The basic architecture reminds me of an FRAM + NAND SSD design that a Korean university presented at the Flash Memory Summit a few years ago. Either approach gets past the problem of using a failure-prone battery, a temperature-sensitive supercap, or a big bulky bank of Continue reading “An ReRAM SSD Design”
Seagate today announced an investment and technology agreement with DensBits, an Israeli SSD controller company mentioned by The SSD Guy in another post.
According to the press release Seagate will use DensBits’ technology for “consumer and enterprise applications including 3 bits/cell (“TLC”) 1Xnm Flash-based consumer-grade SSD, and 2 bits/cell (“MLC”) 1Xnm Flash-based enterprise-grade SSD.”
A pattern is starting to emerge. We understand that Seagate’s current Pulsar SSDs use chips from Link_A_Media (the subject of another recent post) which has only recently Continue reading “Seagate Invests in DensBits”
Link_A_Media, recently graced with a new design win and serious accolades for its new SSD controller, was acquired on June 20 by Korea’s SK Hynix Semiconductor.
According to the Wall Street Journal, SK Hynix paid $248 million for the company.
This is the fourth SSD controller company to be acquired recently:
What’s going on? Why are Continue reading “Link_A_Media Acquired by SK Hynix”
It’s tough to design an SSD controller, and even tougher to make one that can simply compete against the great ones that already ship in volume. To make a truly better controller would seem to require an astonishing effort. It appears that a company with a very odd name: Link_A_Media has done just that.
The company’s first commercial design win in Corsair‘s fourth-generation Neutron Series SSDs was announced at COMPUTEX on June 5th. Corsair’s market focus is high-performance compute hardware aimed at gamers – the company only ships product that can out-perform its competition, and is able to take a higher price thanks to its solid reputation for speed. Getting a first design win at Corsair is a real feather in Link_A_Media’s cap!
But then, today (June 7), Corsair won two Continue reading “Link_A_Media’s Roaring SSD Debut”
DensBits, a flash memory controller company, has just introduced its new DB3610 “Memory Modem” eMMC controller for 3-bit or TLC flash. The controller is the first to use DensBits’ new technology which the company claims can coax better reliability out of 3-bit flash than most controllers can out of 2-bit MLC, to provide important cost savings to OEMs.
Read and write performance is also said to be nearly on a par with 2-bit MLC.
DensBits’ Memory Modem is a blend of Continue reading “DensBits Debuts with eMMC Controller”