Smarter NAND for Better SSDs

NAND part of one of the diagrams below.Micron presented something really interesting during the company’s Investor Day Conference last week, but it didn’t seem to get any press coverage.  The company naturally repeated its plan to become a more important supplier of data center SSDs, but what The SSD Guy was most interested in were a few comments they gave for choosing to make vertically-integrated SSDs.  Micron now makes not only the NAND and the DRAM internal to its SSDs, but also the controller.

Why would a company make its own SSD controller?  After all, a lot of highly-respected SSD controller manufacturers like Silicon Motion, Marvel, and Phison make excellent SSD controllers.  By selling these controllers to more than one SSD maker they will typically produce higher volumes than Micron would use, allowing them to defray their development costs (roughly $50 million) across a larger number of units to shrink the per-unit cost.

Most SSD makers are able to satisfactorily differentiate their SSDs from those of their competitors by fine-tuning the firmware, so there’s rarely a strong competitive reason to design an in-house controller.  This firmware approach has been used with great success for nearly two decades by Solidigm (formerly Intel’s NAND flash & SSD business).

Both Micron and the independent controller makers would use a CMOS logic foundry to manufacture these chips, so there’s no technical advantage there.  Although Micron would capture the profits that would have gone to the controller maker, that’s not usually enough for an SSD maker to profitably offset the development costs.

What Micron said a couple of times during its presentations was that the company is using an in-house controller because a portion of the SSD controller has been incorporated into the NAND flash chips themselves.  When you make your own NAND chips you can do that.  An architectural change this significant would not only simplify the controller, allowing a less expensive design to be used, but a standard controller may not even be able to take advantage of the functions now incorporated within the NAND chips, and this might limit the SSD’s performance.

What Would Go Into the NAND?

Micron didn’t give even the slightest detail of what had been brought into the NAND chip, but let’s guess that it’s a portion of the garbage collection.  That’s the process of consolidating certain partially-valid NAND blocks into a single block to free up another.  It involves moving the valid part of two or more blocks into a third block that has already been erased, then erasing the blocks that the original data came from.

In most SSDs that is done by reading the valid data from one block, then writing it into the erased block, then reading from another block, and writing to the new block, and so forth.  The diagram below is a rough illustration.  All of the data goes through the controller.  After that, the original blocks are erased.  This involves a lot of slow I/O transactions through a relatively narrow bus, even though the internal buses of the NAND chip are thousands of bits wide.

Four block diagrams of a NAND chip (with its internal blocks) and a controller, illustrating the four steps described in the text.

What if there were a way to eliminate all of this I/O?  It could be managed as shown in the diagram below, where the controller simply tells the chip what to move and where to put it, and the NAND chip does the rest, without moving any of the data through the narrower external bus or the controller.

Same block diagrams, but only two steps, moving data directly from block to block within the NAND chip.

Not only would that reduce the bus traffic and accelerate the transfers, since the internal buses are so wide, but it would also limit the controller’s involvement and free it up to manage a larger array or to optimize performance in other ways.  A less-powerful (and cheaper) controller might be able to use these special NAND chips to out-perform SSDs with significantly more elaborate and expensive controllers tied to standard NAND flash.

None of this makes economic sense unless the NAND flash chips can be sold into the broader flash market, so the NAND chip’s share of the control logic can’t be allowed to impede normal operation.  This would tend to make the designers choose only very simple functions.  Also, simpler functions would be less likely to increase the die size and cost of the NAND.  A sufficiently-simple controller might even fit into portions of the silicon that would otherwise go unused.  These garbage-collection primitives would certainly meet that requirement.

Haven’t We Heard of This Before?

Readers of The Memory Guy blog may think that this looks somewhat familiar, after all, a lot of companies are adding processors into DRAM chips to reduce I/O and take advantage of those wide internal buses.  The most recent post about this covered Samsung’s Aquabolt-XL AI processor, which adds a processor to an HBM stack.  The Micron approach is in NAND, though, which is the only NAND-based processor in memory (PIM) that I have heard of.  That seems natural, since NAND flash is so very slow compared to DRAM.  Micron’s ends, though, seem to be significantly more modest: just move a portion of the SSD controller into the NAND, not an entire CPU.

And this would make sense.  In the case of garbage collection, some central authority still needs to be in charge of determining which portions of which blocks to combine and when to combine them, and that central authority would most reasonably be the SSD controller.  The controller, after all, keeps track of the valid and invalid portions of each of the blocks within the NAND chips.  The controller also keeps track of which blocks are erased.

Remember, though, that this is just my idle conjecture.  Micron may be doing something altogether different.  The company’s engineers may have chosen more appropriate functions to pull into the NAND.  In the end, though, the new NAND functions, whatever they are, probably accelerate the SSD while reducing the controller’s complexity and cost.  I would also assume that Micron plans to keep these functions confidential, so that only Micron SSDs can take advantage of them.  This would give the company a distinct competitive edge.

The idea that Micron was able to embed a portion of the controller into its NAND chips is an interesting step that shows that the company doesn’t limit itself to conventional thinking.  Instead of making the NAND chips that are nothing more than NAND, and leaving the controller to manage everything, Micron has put controller primitives into the NAND chip.  Expect to see this approach adopted by other NAND flash makers in the future.

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2 thoughts on “Smarter NAND for Better SSDs”

  1. Interesting. A 3x write amplification implies 2/3rds of data movement could be inside the chip, a bonus for power and throughput. It does, however, require the ECC functionality to be provided on the NAND chip since it is important to regenerate clean data. Historically that functionality has been on the controllers. It might be feasible to partially offload it (for example, compute the syndrome on the chip but locate the correction using more advanced logic in the controller, while the syndrome movement might be much smaller than the whole data).

    If they are really scaling up for CIM, though, they might be pathfinding to get to a place where they can do things like JSON parsing, scanning, field extraction and insertion, close enough to the chip to save more time and energy.

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