Tag: Chuo University

Extreme SSD Error Correction

Chuo University EmblemAt last week’s International Solid State Circuits Conference (ISSCC) Shuhei Tanakamaru, a researcher from Japan’s Chuo University, detailed a scheme to reduce MLC SSD bit error rates (BER) by 32 times over conventional techniques.  The approach used an impressive combination of mirroring, vertical and horizontal error correction, and a deep understanding of the most likely kinds of bit errors flash will experience.

This is a very novel and well-conceived technique that may find industry adoption in future SSDs.

The steps included in the paper are used in addition to the Continue reading “Extreme SSD Error Correction”

An ReRAM SSD Design

Chuo University EmblemA colleague pointed The SSD Guy to an ExtremeTech article about researchers at Japan’s Chuo University who have designed an SSD that uses a resistive RAM (ReRAM) as a buffer and is built using TSV technology.  The design was presented at the IEEE’s 2012 Symposium on VLSI Circuits this month in Hawaii.  A Nikkei article gives additional information.

The basic architecture reminds me of an FRAM + NAND SSD design that a Korean university presented at the Flash Memory Summit a few years ago.  Either approach gets past the problem of using a failure-prone battery, a temperature-sensitive supercap, or a big bulky bank of Continue reading “An ReRAM SSD Design”