This post is the second of a two-part SSD Guy series outlining the nonvolatile DIMM or NVDIMM. The first part explained what an NVDIMM is and how they are named. This second part describes the software used to support NVDIMMs (BIOS, operating system, and processor instructions) and discusses issues of security.
Today’s standard software boots a computer under the assumption that the memory at boot-up contains random bits — this needed to be changed to support NVDIMMs. The most fundamental of these changes was to the BIOS (Basic I/O Subsystem), the code that “wakes up” the computer.
The BIOS is responsible for detecting all of the computer’s hardware and installing the appropriate drivers, after which it loads the bootstrap program from the mass storage device into the DRAM main memory. When an NVDIMM is used the BIOS must Continue reading “An NVDIMM Primer (Part 2 of 2)”
NVDIMMs are gaining interest lately, so The SSD Guy thought it might be worthwhile to explain both what they are and how NVDIMM nomenclature works.
As I was writing it I noticed that the post got pretty long, so I have split it into two parts. The first part explains what an NVDIMM is and defines the names for today’s three kinds of NVDIMM. The second part tells about software changes used to support NVDIMMs in BIOS, operating systems, and even processor instruction sets. It also discusses the problem of security.
In case the name is unfamiliar, NVDIMM stands for “Nonvolatile Dual-Inline Memory Module.” Standard computer memory – DRAM – is inserted into the system in the DIMM form factor, but DRAM loses its data when power is removed. The NVDIMM is nonvolatile, or persistent, so its data remains intact despite a loss of power. This takes some effort and always costs more for reasons that will be explained shortly.
Although might seem a little odd to discuss memory in a forum devoted to SSDs, which are clearly storage, the NVDIMM is a storage device, so it rightly Continue reading “An NVDIMM Primer (Part 1 of 2)”
I have just added a new white paper onto the Objective Analysis website: Matching Flash to the Processor – Why Multithreading Needs Parallelized Flash.
This document examines the evolution of today’s CPUs, whose clock frequencies have stopped increasing, but now exploit parallelism to scale performance. Multiple DRAM channels have also been added to performance computing to add parallelism to the memory channel.
Storage hasn’t kept pace with this move to parallelism and that is limiting today’s systems.
New NAND flash DIMMs recently introduced by Diablo, SanDisk, and IBM, provide a reasonable approach to adding parallel flash to a system on the its fastest bus – the memory channel. This white paper shows that storage can be scaled to match the processor’s growing performance by adding flash DIMMs to each of the many DRAM buses in a performance server.
The white paper is downloadable for free from the Objective Analysis home page. Have a look.
On Thursday IBM announced its X6 product family, the sixth generation of the company’s successful EXA server architecture. A smaller byline of the introduction was the company’s new eXFlash memory-channel storage or eXFlash DIMM which is offered as one of many flash options available to X6 users.
Close followers of The SSD Guy already know that I am a serious advocate of putting flash onto the memory bus. Why slow the technology down by Continue reading “IBM Launches Flash DIMMs”
Today NAND flash is being shoehorned into HDD formats simply because it is persistent – the data doesn’t disappear when the lights go out. This approach fails to take advantage of NAND’s greatest strength – its low cost relative to DRAM – and this prevents it from fully meeting the needs of most data centers.
Since 2004 NAND has been cheaper than DRAM, and today its price per gigabyte is an order of magnitude lower than that of DRAM. NAND is cheaper and slower than DRAM, and HDD is cheaper and slower than NAND.
A role better suited to NAND flash technology is Continue reading “White Paper: Using Flash as Memory”
Diablo Technology has just introduced a new set of DIMMs that put flash memory right onto the DDR3 memory bus.
I can already hear readers saying: “Wait! You can’t do that!” Well, you’re right, but the new module comes awfully close to that by putting the NAND behind an ASIC that interfaces between the DDR3 bus and the NAND.
Why do this? Quite simply because you can get more “Bang for the Buck” by adding NAND to the system once you’ve reached a certain DRAM size. The Diablo “Memory Channel Storage” (MCS) approach supports the addition of terabytes of NAND at the loss of Continue reading “Diablo: Flash Belongs on the Bus”