Tag: External Data Buffering

How Controllers Maximize SSD Life – External Data Buffering

Tempus FugitSince NAND flash is weakened by erase/write cycles then it would make sense to try to reduce those cycles to prolong the life of an SSD right?  That’s what external data buffers are designed to do.

There are many ways to use RAM (either a RAM internal to the SSD controller chip or a discrete DRAM chip on the SSD’s printed circuit card) to stage data in a way that will reduce erase/write cycles.

One is to perform a function called “Write Coalescing.”  This involves Continue reading “How Controllers Maximize SSD Life – External Data Buffering”

How Controllers Maximize SSD Life

Tempus FugitHow do controllers maximize the life of an SSD?  After all, MLC flash has a lifetime of only 10,000 erase/write cycles or fewer and that is a very small number compared to the write traffic an SSD is expected to see in a high-workload environment, especially in the enterprise.  Still, MLC is becoming the norm in the enterprise.

How do they do that?

This is where SSD architects really earn their pay.  There are eight basic techniques that The SSD Guy knows of to extend SSD life beyond Continue reading “How Controllers Maximize SSD Life”