The Storage Developer Conference in September gave a rare glimpse into two very different directions that SSD architectures are pursuing. While some of the conference’s presentations touted SSDs with increasing processing power (Eideticom, NGD, Samsung, and ScaleFlux) other presentations advocated moving processing power out of the SSD and into the host server (Alibaba, CNEX, and Western Digital).
Why would either of these make sense?
A standard SSD has a very high internal bandwidth that encounters a bottleneck as data is forced through a narrower interface. It’s easy to see that an SSD with 20+ NAND chips, each with an 8-bit interface, could access all 160 bits simultaneously. Since there’s already a processor inside the SSD, why not open it to external programming so that it can perform certain tasks within the SSD itself and harness all of that bandwidth?
Example tasks would include Continue reading “SSDs Need Controllers with More, NO! Less Power”
Last Monday, May 21, Micron introduced the industry’s first QLC SSD for enterprise applications. Micron’s press release is HERE.
Although this is a laudatory feat, the industry has been headed in this direction for a number of years. In fact, this was the subject of a presentation that I made to the Storage Networking Industry Association (SNIA) during its Winter Symposium in January 2014.
The slide in which I discussed this appears as this post’s graphic. (Click on it to see a larger rendition.) This table attempted to illustrate that all SSDs were headed towards TLC (and implicitly QLC) over the long term despite the fact that naysayers persistently argued that this could never happen. It looks at attitudes over history and considers the fact that things that the industry said could “Never” happen ended up eventually becoming the mainstream technology.
Since I live, eat, and breathe Continue reading “The Micron QLC SSD – No Surprises Here”
A few years ago The SSD Guy posted an analogy that Intel’s Jim Pappas uses to illustrate the latency differences between DRAM, an SSD, and an HDD. If we look at DRAM latency to be a single heartbeat, then what happens when we scale that timing up to represent SSDs and HDDs? How many heartbeats would it take to access either one, and what could you do in that time?
I still think it’s a pretty interesting way to make all these latency differences easier to understand.
Just recently I learned of a Rich Report video of a 2015 presentation in which Micron’s Ryan Baxter uses a different and equally interesting analogy based on tomatoes.
Tomatoes aren’t the first thing that comes to my mind when I think about SSDs, but this video may change my way of thinking!
The tomato slide, 9:30 into the presentation, is Continue reading “Comparing SSDs to Tomatoes”
This post is the second of a two-part SSD Guy series outlining the nonvolatile DIMM or NVDIMM. The first part explained what an NVDIMM is and how they are named. This second part describes the software used to support NVDIMMs (BIOS, operating system, and processor instructions) and discusses issues of security.
Today’s standard software boots a computer under the assumption that the memory at boot-up contains random bits — this needed to be changed to support NVDIMMs. The most fundamental of these changes was to the BIOS (Basic I/O Subsystem), the code that “wakes up” the computer.
The BIOS is responsible for detecting all of the computer’s hardware and installing the appropriate drivers, after which it loads the bootstrap program from the mass storage device into the DRAM main memory. When an NVDIMM is used the BIOS must Continue reading “An NVDIMM Primer (Part 2 of 2)”
NVDIMMs are gaining interest lately, so The SSD Guy thought it might be worthwhile to explain both what they are and how NVDIMM nomenclature works.
As I was writing it I noticed that the post got pretty long, so I have split it into two parts. The first part explains what an NVDIMM is and defines the names for today’s three kinds of NVDIMM. The second part tells about software changes used to support NVDIMMs in BIOS, operating systems, and even processor instruction sets. It also discusses the problem of security.
In case the name is unfamiliar, NVDIMM stands for “Nonvolatile Dual-Inline Memory Module.” Standard computer memory – DRAM – is inserted into the system in the DIMM form factor, but DRAM loses its data when power is removed. The NVDIMM is nonvolatile, or persistent, so its data remains intact despite a loss of power. This takes some effort and always costs more for reasons that will be explained shortly.
Although might seem a little odd to discuss memory in a forum devoted to SSDs, which are clearly storage, the NVDIMM is a storage device, so it rightly Continue reading “An NVDIMM Primer (Part 1 of 2)”
This Sunday (Sept. 20, 2015) I will be presenting my company’s findings on the 3D XPoint memory that was introduced by Intel and Micron in July. I will be speaking at the Storage Networking Industry Association (SNIA) Storage Developer Conference (SDC) Pre-Conference Primer. You can click the name to be taken to the agenda.
This won’t be the only talk about persistent memory technology at the conference. Prior to my presentation storage consultants Tom Coughlin and Ed Grochowski will give an overview of advances in nonvolatile memories, and following my presentation will be two Intel talks.
Intel will be covering this new technology a lot during the conference. Of a total of 120 presentations at the conference and pre-conference primer, Intel will be presenting nine, seven of which directly name persistent memory or nonvolatile memory in the title. Other firms will also be talking about NVM: AgigA, Calypso, HP, Pure Storage, and SMART Modular. Even Microsoft alludes to it in a couple of its presentation titles. Persistent memory is a hot issue.
So, the question for readers of The SSD Guy blog is: “Will this do away with SSDs?”
This is a question that was Continue reading “3D XPoint Memory at the Storage Developer’s Conference”
There’s been a lot of interest in NVRAM recently. This technology has been lurking in the background for decades, and suddenly has become very popular.
What is NVRAM? Quite simply, it’s DRAM or SRAM that has a back-up flash memory a small controller, and a battery or super-capacitor. During operation the DRAM or SRAM is used in a system the same way that any DRAM or SRAM would be used. When power is interrupted the controller moves all of the data from the DRAM or SRAM to the flash using the backup power from the battery or super-capacitor. When power is restored, the controller moves the contents of the flash back into the SRAM or DRAM and the processor can resume operation where it left off.
In some ways it’s storage and in some ways it’s memory, so Continue reading “Where does NVRAM Fit?”
Violin Memory and Microsoft have jointly announced a novel way of harnessing the power of Windows Server software. Violin will be shipping its memory arrays with a special version of Windows Server 2012 R2 pre-installed on the embedded server that manages the internal operations of Violin’s all-flash array.
Violin explains that native support of specially-optimized versions of Windows Server and System Center that have been tuned for an all-memory array will provide improved performance and economics for large-scale enterprise cloud deployments.
The system can internally run Continue reading “Violin & Microsoft Take a New Approach to Scaling”
In his Flash Memory Summit keynote on Wednesday, Micron VP and Chief Memory Systems Architect Ed Doller made a compelling demonstration of the power and performance advantages of a new approach to computing.
With true showmanship, Doller had his co-workers hand out buttons with LED lights to the entire audience. The LEDs in these buttons were either green or blue, with the colors randomly dispersed among the crowd. Doller asked the entire audience to turn on their lights, then called one row of the audience to file up to the stage so he could determine whether each person’s button was blue or green.
He pointed out that this was like having a single CPU check the contents of a drive. He then asked why things should work this way – wouldn’t it be more sensible to Continue reading “A New Way to Use SSDs”
Today NAND flash is being shoehorned into HDD formats simply because it is persistent – the data doesn’t disappear when the lights go out. This approach fails to take advantage of NAND’s greatest strength – its low cost relative to DRAM – and this prevents it from fully meeting the needs of most data centers.
Since 2004 NAND has been cheaper than DRAM, and today its price per gigabyte is an order of magnitude lower than that of DRAM. NAND is cheaper and slower than DRAM, and HDD is cheaper and slower than NAND.
A role better suited to NAND flash technology is Continue reading “White Paper: Using Flash as Memory”