NVMe

High Availability in an m.2 Format

Photo of finger pusing on hinge in center of m.2 HA SSDThe m.2 SSD format has become wildly successful in the data center for use as a boot drive and even in SSD arrays.  The m.2 format supports either the SATA or the NVMe interface,  Something that has been missing, however, is a version of this format for high-availability (HA) systems.  These are mission-critical systems that cannot fail, no matter what.

Until today HA systems had to use the SAS interface which supports two independent ports, or the new dual-port NVMe SSDs that come in either a 2.5″ U.2 or the AIC format.  Both of these offer redundant ports but, unfortunately, both U.2 and AIC SSDs are considerably larger than the m.2 format.

Despite its small size m.2 has so far not been considered as a candidate for dual-port SSDs.  This is because the m.2 format uses a card edge connection it must be inserted by sliding the narrow end of the card into the socket.  A dual-port version needs to have connectors at both narrow ends, making it impossible to plug the SSD into a pair of board-mounted sockets.

Today a revolutionary new company called Kowabunga Data is introducing its ingenious solution to the problem.  Yes, it is indeed an Continue reading

What is an SSD Trim Command?

TrimmerAlthough the Trim command has been defined for nearly a decade, for some reason I have never written a post to explain it.  It’s time for that to change.

Trim is something that was never required for HDDs, so it was a new command that was defined once SSDs became prevalent.  The command is required because of one of those awkward encumbrances that NAND users must accommodate: Erase before write.

NAND flash bits cannot be altered the same way as an HDD.  In an HDD a bit that’s currently set to a “1” can be re-written to a “0” and vice versa.  Writing a bit either way takes the same amount of time.  In NAND flash a 1 can be written to a zero, but the opposite is not the case.  Instead, the entire block (4-16k bytes) must be erased at once, after which all bits are set to a 1.  Once that has been done then zeros can be written into that block to store data.  An erase is an excruciatingly slow operation, taking up to a half second to perform.  Writes are faster, but they’re still slow.

Let’s say that a program needs to Continue reading

OCZ Comes Roaring Back with NVMe SSD Debut

The OCZ Z-Drive 6000It’s really something to see a company recover from a big challenge, and signs of that happened this week with OCZ’s introduction of a new NVMe-based PCIe SSD they call the Z-Drive 6000 series.

This replacement for the company’s Z-Drive 4000 series is a complete redesign with an obsession for performance.  OCZ tells me that they moved from a 2-hop design to a 1-hop by using the PMC Princeton PCIe SSD controller, and have passed the University of New Hampshire Interoperability Labs’ compliance tests to NVMe 1.1B compliance.

But how does it perform?  Well the 1-hop design helps reduce latency (which is just starting to overshadow IOPS in users’ minds) and the latency of this SSD is significantly lower than competing NVMe SSDs: between 25-30μs, figures that OCZ tells me are very consistent, a big plus for enterprise applications.  As for IOPS, the device can perform under a 70/30 Read/Write load at 330K.

The 6000 series is provided in both standard MLC and eMLC for those who want the security of eMLC and are willing to sacrifice a little performance to sleep better at night.

This product is a good fit for the market needs, and shows how devoted OCZ and its parent Toshiba are to providing high performance in the SSD marketplace.