At last month’s SNIA Persistent Memory Summit Oracle presenter Jia Shi, Sr. Director of Exadata Development, shared some statistics on the Exadata system’s history over the past ten years. (Click on the graphic to the left to see the timeline.) The speaker highlighted the fact that the system’s I/O performance has grown from 0.05 million IOPS ten years ago to 16 million IOPS today, a 320X improvement! Shi said that Continue reading “Does Persistent Memory Improve Performance? Ask Oracle!”
On Tuesday, January 14, Tom Coughlin and I were featured in a BrightTalk webinar hosted by the Storage Networking Industry Association (SNIA). A recording of this webinar has been posted so that you can view it at your convenience.
This webinar looks at emerging memories and where they now stand, giving a Continue reading “SNIA Webcast: Emerging Memories”
This post is the second of a two-part SSD Guy series outlining the nonvolatile DIMM or NVDIMM. The first part explained what an NVDIMM is and how they are named. This second part describes the software used to support NVDIMMs (BIOS, operating system, and processor instructions) and discusses issues of security.
Today’s standard software boots a computer under the assumption that the memory at boot-up contains random bits — this needed to be changed to support NVDIMMs. The most fundamental of these changes was to the BIOS (Basic I/O Subsystem), the code that “wakes up” the computer.
The BIOS is responsible for detecting all of the computer’s hardware and installing the appropriate drivers, after which it loads the bootstrap program from the mass storage device into the DRAM main memory. When an NVDIMM is used the BIOS must Continue reading “An NVDIMM Primer (Part 2 of 2)”
What is NVRAM? Quite simply, it’s DRAM or SRAM that has a back-up flash memory a small controller, and a battery or super-capacitor. During operation the DRAM or SRAM is used in a system the same way that any DRAM or SRAM would be used. When power is interrupted the controller moves all of the data from the DRAM or SRAM to the flash using the backup power from the battery or super-capacitor. When power is restored, the controller moves the contents of the flash back into the SRAM or DRAM and the processor can resume operation where it left off.
In some ways it’s storage and in some ways it’s memory, so Continue reading “Where does NVRAM Fit?”
I have just added a new white paper onto the Objective Analysis website: Matching Flash to the Processor – Why Multithreading Needs Parallelized Flash.
This document examines the evolution of today’s CPUs, whose clock frequencies have stopped increasing, but now exploit parallelism to scale performance. Multiple DRAM channels have also been added to performance computing to add parallelism to the memory channel.
Storage hasn’t kept pace with this move to parallelism and that is limiting today’s systems.
New NAND flash DIMMs recently introduced by Diablo, SanDisk, and IBM, provide a reasonable approach to adding parallel flash to a system on the its fastest bus – the memory channel. This white paper shows that storage can be scaled to match the processor’s growing performance by adding flash DIMMs to each of the many DRAM buses in a performance server.
The white paper is downloadable for free from the Objective Analysis home page. Have a look.
Viking Technology on Wednesday announced that the company has arranged with SuperMicro to deliver solutions that should solve issues key to flash storage array designers. Supermicro will ship server boards that have all the hooks necessary to support Viking’s nonvolatile DDR3 DIMMs without users having to wait for this kind of support to arrive in servers based on the standard Intel platform.
Viking’s marketing folks tell me that NV-DIMM support is something that its customers have been asking for, and that it will be a standard component of Continue reading “Viking: Why Wait for Nonvolatile DRAM?”