Those who have been reading posts on The SSD Guy blog for some time have often heard me explain that SSD prices will not fall below HDD prices anytime soon. Last week Western Digital shared a roadmap that shows that we can expect for there to be a sizeable price gap between the two technologies at least through 2028.
Let me stop for a moment to point out that Western Digital Corp, or WDC, no longer has any reason to take sides in the HDD vs. SSD battle now that the company has acquired SanDisk, a leading SSD maker. Even before that, WDC’s HGST business has been the market leader in SAS SSDs for a number of years. WDC doesn’t take sides in arguments about SSDs vs. HDDs. Instead the company stands ready to sell whichever one the customer finally decides to use.
This post’s graphic comes from a chart that WDC used on October 11 when introducing its new MAMR head technology, which the company expects to propel HDD capacities up, and HDD price per terabyte down, for a number of years. To create this chart WDC’s HDD team joined forces with the SanDisk flash team to project both HDD and NAND price per terabyte for the next 11 years. The most important conclusion is that Continue reading “WDC: No SSD/HDD Crossover”
From time to time IT managers ask The SSD Guy if there’s an easy way to compare SSDs made with MLC flash against those made using eMLC flash. Most folks understand that eMLC flash is a less costly alternative to SLC flash, both of which provide longer wear than standard MLC flash, but not everyone realizes that eMLC’s superior endurance comes at the cost of slower write speed. By writing to the flash more gently the technology can be made to last considerably longer.
So how do you compare the two? OCZ introduced MLC and eMLC versions of the same SSD this week, and this provides a beautiful opportunity to explore the difference.
As you would expect, the read parameters are all identical. This stands to reason, since Continue reading “MLC vs. eMLC – What’s the Difference?”
Someone recently asked The SSD Guy if there is a way to determine whether an SSD is SLC, MLC, eMLC or TLC.
I found it a little odd to be asked this, since most vendors tell what kind of flash they use in an SSD’s specifications, especially if it’s SLC.
Not finding it there then the next thing I would look at is the price. Raw SLC NAND flash now sells for about 6-10 times as much as its MLC counterpart, so an SSD with a price of around $1/GB is likely to be MLC and one that sells for around $10/GB is probably SLC.
TLC SSDs are really rare. There is the Continue reading “What’s In My SSD? SLC, MLC, or TLC?”
Given that you have used all those other forms of improving SSD wear that we have discussed so far, but you still don’t find that this is enough, what do you do next? Well a few SSD controllers go one step further and manage some of the inner workings of the NAND flash chip itself.
If that sounds like a significant undertaking to you, then you clearly understand why so very few controllers take this approach. The information used to perform this function is not generally available – it takes a special relationship with the NAND flash supplier – and you can’t develop this relationship unless the NAND supplier Continue reading “How Controllers Maximize SSD Life – Internal NAND Management”
One way that SSD controllers maximize the life of an SSD is to use feedback on the life of flash blocks to determine how wear has impacted them. Although this used to be very uncommon, it is now being incorporated into a number of controllers.
Here’s what this is all about: Everybody knows that endurance specifications tell how much life there is in a block, right? For SLC it is typically 100,000 erase/write cycles, and for MLC it can be as high as 10,000 cycles (for older processes) but goes down to 5,000 or even 3,000 for newer processes. TLC endurance can be in the hundreds of cycles. Now the question is: “What happens after that?”
In most cases individual bits start to Continue reading “How Controllers Maximize SSD Life – Feedback on Block Wear”
Over provisioning is one of the most common ways that SSD designers can help assure that an SSD has a longer life than the flash’s endurance rating would support. If an SSD contains more flash than is presented at its interface, the controller can manage wear across a larger number of blocks while at the same time accelerating disk performance by moving slow operations like block erases out of the way of the SSD’s key functions.
Many people like to compare wear leveling to rotating a car’s tires. In this vein, think of over provisioning as having a bunch of spare Continue reading “How Controllers Maximize SSD Life – Over Provisioning”
Write amplification plays a critical role in maximizing an SSD’s usable life. The lower the write amplification, the longer the SSD will last. SSD architects pay special attention to this aspect of controller design.
Unlike the other factors described in this series this is not a technique that extends flash life beyond the 10,000 erase/write cycles that one would normally expect to result in a failure, but it is very important to SSD longevity.
Write Amplification is sufficiently complex that I won’t try to define it in this post, but Continue reading “How Controllers Maximize SSD Life – Reduced Write Amplification”
There are more advanced means than simple error correction to help remove bit errors in NAND flash and those will be the subject of this post. The general term for this approach is “DSP” although it seems to have very little to do with the kind of DSP algorithm used to perform filtering or build modem chips.
While ECC corrects errors without knowing how they got there, DSP helps to correct any of the more predictable errors that are caused by internal error mechanisms that are inherent to the design of the chip. A prime example of such an error would be adjacent cell disturb.
Here’s a brief explanation of Continue reading “How Controllers Maximize SSD Life – Other Error Management”
Error correction (ECC) can have a very big impact on the longevity of an SSD, although few understand how such a standard item can make much difference to an SSD’s life. The SSD Guy will try to explain it in relatively simple terms here.
All NAND flash requires ECC to correct random bit errors (“soft” errors.) This is because the inside of a NAND chip is very noisy and the signal levels of bits passed through a NAND string are very weak. One of the ways that NAND has been able to become the cheapest of all memories is by requiring error correction external to the chip.
This same error correction also helps to correct bit errors due to wear. Wear can cause bits to become stuck in one state or the other (a “hard” error), and it can increase the frequency of soft errors.
Although it is not widely Continue reading “How Controllers Maximize SSD Life – Improved ECC”
Since NAND flash is weakened by erase/write cycles then it would make sense to try to reduce those cycles to prolong the life of an SSD right? That’s what external data buffers are designed to do.
There are many ways to use RAM (either a RAM internal to the SSD controller chip or a discrete DRAM chip on the SSD’s printed circuit card) to stage data in a way that will reduce erase/write cycles.
One is to perform a function called “Write Coalescing.” This involves Continue reading “How Controllers Maximize SSD Life – External Data Buffering”