The Micron QLC SSD – No Surprises Here

Progression of SSDsLast Monday, May 21, Micron introduced the industry’s first QLC SSD for enterprise applications.  Micron’s press release is HERE.

Although this is a laudatory feat, the industry has been headed in this direction for a number of years.  In fact, this was the subject of a presentation that I made to the Storage Networking Industry Association (SNIA) during its Winter Symposium in January 2014.

The slide in which I discussed this appears as this post’s graphic.  (Click on it to see a larger rendition.)  This table attempted to illustrate that all SSDs were headed towards TLC (and implicitly QLC) over the long term despite the fact that naysayers persistently argued that this could never happen.  It looks at attitudes over history and considers the fact that things that the industry said could “Never” happen ended up eventually becoming the mainstream technology.

Since I live, eat, and breathe Continue reading “The Micron QLC SSD – No Surprises Here”

WDC: No SSD/HDD Crossover

WDC HDD vs NAND Price per GB 10X GapThose who have been reading posts on The SSD Guy blog for some time have often heard me explain that SSD prices will not fall below HDD prices anytime soon.  Last week Western Digital shared a roadmap that shows that we can expect for there to be a sizeable price gap between the two technologies at least through 2028.

Let me stop for a moment to point out that Western Digital Corp, or WDC, no longer has any reason to take sides in the HDD vs. SSD battle now that the company has acquired SanDisk, a leading SSD maker.  Even before that, WDC’s HGST business has been the market leader in SAS SSDs for a number of years.  WDC doesn’t take sides in arguments about SSDs vs. HDDs.  Instead the company stands ready to sell whichever one the customer finally decides to use.

This post’s graphic comes from a chart that WDC used on October 11 when introducing its new MAMR head technology, which the company expects to propel HDD capacities up, and HDD price per terabyte down, for a number of years.  To create this chart WDC’s HDD team joined forces with the SanDisk flash team to project both HDD and NAND price per terabyte for the next 11 years.  The most important conclusion is that Continue reading “WDC: No SSD/HDD Crossover”

What’s In My SSD? SLC, MLC, or TLC?

SLC, MLC, or TLC?Someone recently asked The SSD Guy if there is a way to determine whether an SSD is SLC, MLC, eMLC or TLC.

I found it a little odd to be asked this, since most vendors tell what kind of flash they use in an SSD’s specifications, especially if it’s SLC.

Not finding it there then the next thing I would look at is the price.  Raw SLC NAND flash now sells for about 6-10 times as much as its MLC counterpart, so an SSD with a price of around $1/GB is likely to be MLC and one that sells for around $10/GB is probably SLC.

TLC SSDs are really rare.  There is the Continue reading “What’s In My SSD? SLC, MLC, or TLC?”

Comparing Samsung’s Planar and V-NAND SSDs

Samsung 3D V-NAND Press PhotoSamsung recently introduced  its 3D V-NAND-based 850 SSD which, according to The Tech Report, uses the same MEX controller as the company’s 3-bit planar SSD, the 840, introduced last year.

Samsung said in its keynote speech at the 2013 Flash Memory Summit that V-NAND consumes an average of 27% less power and runs at least 20% faster than its planar counterpart in an SSD application, all while providing ten times the endurance.  It’s only natural to assume that this would allow designers to produce a V-NAND SSD that would significantly outperform its planar NAND counterpart.

The SSD Guy had an opportunity to review Continue reading “Comparing Samsung’s Planar and V-NAND SSDs”

How Controllers Maximize SSD Life – Internal NAND Management

Tempus FugitGiven that you have used all those other forms of improving SSD wear that we have discussed so far, but you still don’t find that this is enough, what do you do next?  Well a few SSD controllers go one step further and manage some of the inner workings of the NAND flash chip itself.

If that sounds like a significant undertaking to you, then you clearly understand why so very few controllers take this approach.  The information used to perform this function is not generally available – it takes a special relationship with the NAND flash supplier – and you can’t develop this relationship unless the NAND supplier Continue reading “How Controllers Maximize SSD Life – Internal NAND Management”

How Controllers Maximize SSD Life – Feedback on Block Wear

Tempus FugitOne way that SSD controllers maximize the life of an SSD is to use feedback on the life of flash blocks to determine how wear has impacted them.  Although this used to be very uncommon, it is now being incorporated into a number of controllers.

Here’s what this is all about: Everybody knows that endurance specifications tell how much life there is in a block, right?  For SLC it is typically 100,000 erase/write cycles, and for MLC it can be as high as 10,000 cycles (for older processes) but goes down to 5,000 or even 3,000 for newer processes.  TLC endurance can be in the hundreds of cycles.  Now the question is: “What happens after that?”

In most cases individual bits start to Continue reading “How Controllers Maximize SSD Life – Feedback on Block Wear”

How Controllers Maximize SSD Life – Over Provisioning

Tempus FugitOver provisioning is one of the most common ways that SSD designers can help assure that an SSD has a longer life than the flash’s endurance rating would support.  If an SSD contains more flash than is presented at its interface, the controller can manage wear across a larger number of blocks while at the same time accelerating disk performance by moving slow operations like block erases out of the way of the SSD’s key functions.

Many people like to compare wear leveling to rotating a car’s tires.  In this vein, think of over provisioning as having a bunch of spare Continue reading “How Controllers Maximize SSD Life – Over Provisioning”

How Controllers Maximize SSD Life – Reduced Write Amplification

Tempus FugitWrite amplification plays a critical role in maximizing an SSD’s usable life.  The lower the write amplification, the longer the SSD will last.  SSD architects pay special attention to this aspect of controller design.

Unlike the other factors described in this series this is not a technique that extends flash life beyond the 10,000 erase/write cycles that one would normally expect to result in a failure, but it is very important to SSD longevity.

Write Amplification is sufficiently complex that I won’t try to define it in this post, but Continue reading “How Controllers Maximize SSD Life – Reduced Write Amplification”

How Controllers Maximize SSD Life – Other Error Management

Tempus FugitThere are more advanced means than simple error correction to help remove bit errors in NAND flash and those will be the subject of this post.  The general term for this approach is “DSP” although it seems to have very little to do with the kind of DSP algorithm used to perform filtering or build modem chips.

While ECC corrects errors without knowing how they got there, DSP helps to correct any of the more predictable errors that are caused by internal error mechanisms that are inherent to the design of the chip.  A prime example of such an error would be adjacent cell disturb.

Here’s a brief explanation of Continue reading “How Controllers Maximize SSD Life – Other Error Management”

How Controllers Maximize SSD Life – Improved ECC

Tempus FugitError correction (ECC) can have a very big impact on the longevity of an SSD, although few understand how such a standard item can make much difference to an SSD’s life.  The SSD Guy will try to explain it in relatively simple terms here.

All NAND flash requires ECC to correct random bit errors (“soft” errors.)  This is because the inside of a NAND chip is very noisy and the signal levels of bits passed through a NAND string are very weak.  One of the ways that NAND has been able to become the cheapest of all memories is by requiring error correction external to the chip.

This same error correction also helps to correct bit errors due to wear.  Wear can cause bits to become stuck in one state or the other (a “hard” error), and it can increase the frequency of soft errors.

Although it is not widely Continue reading “How Controllers Maximize SSD Life – Improved ECC”